The present invention relates to a semiconductor memory device and a refresh control circuit, and more particularly to a semiconductor memory device, wherein a memory cell array comprises the same memory cells as DRAM (dynamic random access memory), and the semiconductor memory device is operable in the same specification as SRAM (static random access memory), and the semiconductor memory device is compatible to SRAM, where a write enable signal, which decides a timing of writing to a memory cell, is non-synchronously given to a write address, and a refresh control circuit for controlling a refresh operation.
SRAM and DRAM are most typical ones of semiconductor memory devices which accept random accesses. As compared to DRAM, in general, SRAM exhibits a high speed operation. Further, supplying a power to SRAM and entry of an address into the same are sufficient for enabling SRAM to detect any address transition and cause an internal sequencer circuit to operate for performing read and write operations. SRAM may be operable based on input signals with more simple waveforms as compared to DRAM. This allows simplifying a configuration of a circuit which generates the input signal with such the waveform.
SRAM does not need refresh operation, which is needed for DRAM to hold data in the memory cells in DRAM, for which reason managing SRAM is easier. SRAM is advantageous in that a small current is needed for holding data in a stand-by state due to no need for the refresh operation. For those reasons, SRAM has widely been used in a variety of application. In general, SRAM, however, needs six transistors for one memory cell, for which reason a chip of SRAM is larger in size than DRAM, and thus SRAM is higher in price than DRAM.
Meanwhile, DRAM is supplied with a row address and a column address separately or at different two timings, wherein there are needed RAS (row address strobe) and CAS (column address strobe) which define separate timings of capturing the row address and the column address, respectively. Further, a control circuit is needed for cyclically refreshing memory cells. DRAM is more complicated than SRAM in view of timing controls.
DRAM also has a problem with a larger current consumption due to the need for refreshing memory cells even when no external access is made. Notwithstanding, the memory cell of the DRAM may comprise a single capacitor and a single transistor. This makes it relatively easy to achieve a large memory capacity with a small chip size. DRAM is more cheaper than SRAM, provided that the required memory capacity is the same.
SRAM is the main-stream of the semiconductor memory device which is utilized in a portable device, typically, a portable telephone device. This reason is as follows. The past portable telephone device does not need a semiconductor memory device with a large capacity because the past portable telephone device has simple functions. SRAM is more simple in timing control operation than DRAM. SRAM has a smaller current consumption in the stand-by state, for which reason SRAM is more suitable for the portable telephone device which is needed to prolong a continuous communication time and a continuous stand-by time as many as possible.
Recently, however, an advanced portable telephone device has a variety of function, for example, a function of transmitting and receiving e-mails, and another function of making an access to a variety of site for obtaining informations about restaurants. A very recent portable telephone device is also incorporated with a function of making an access to a Web-server on the Internet and displaying summarized contents of a home page. In the future, the portable telephone device may be expected to make accesses to home pages on the Internet similarly to the present desk top type personal computer.
In order to realize those functions, a simple display in text format by the conventional portable telephone device is insufficient but a graphic display for providing a variety of multi-media information to users is essential. It is necessary for this purpose that a large mount of data received from a public network is temporarily stored in the semiconductor memory device in the portable telephone device. It is essential that the semiconductor memory device integrated in the portable device has a large capacity such as DRAM. It is absolute that the portable device has a small size and a light-weight, for which reason it is necessary that the capacity of the semiconductor memory device is increased without increasing the size and the weight.
As described above, SRAM is preferable in view of easy operation and power consumption of the semiconductor memory device integrated in the portable device. DRAM is preferable in view of large capacity. Namely, a semiconductor memory device taking both advantages of SRAM and DRAM is optimum for those portable devices. A semiconductor memory device of this kind so called as xe2x80x9cpseudo SRAMxe2x80x9d has already been considered, wherein the same memory cells are used as those of DRAM, while the specification is almost the same as that used for DRAM in an external view.
The pseudo SRAM does not need to perform such a separate supply of a row address and a column address as conducted in DRAM, for which reason the pseudo SRAM does not need timings signals such as RAS and CAS. The pseudo SRAM may perform a batch-supply of addresses similarly to the general-purpose SRAM. The pseudo SRAM takes the addresses therein by triggering a chip enable signal for read/write operations, wherein the chip enable signal corresponds to a clock of a semiconductor memory device operable synchronizing with the clock signal.
The pseudo SRAM is not necessarily complete-compatible to the general-purpose SRAM. The majority of the pseudo SRAM is provided with refresh control terminals for externally controlling refreshes of memory cells. The external control to the refresh of the pseudo SRAM is needed. The majority of the pseudo SRAM is not easy in operation as compared to SRAM, and needs an additional circuit for refresh control. Another pseudo SRAM has been proposed which is operable in the completely similar specification to the general-purpose SRAM, without external control to the refresh of the pseudo SRAM. This pseudo SRAM also has the following disadvantages.
For writing data into the general-purpose SRAM, generally, an access address is designated as an external address, and subsequently, a write enable signal is activated to give a write instruction. Data to be written are supplied, and input data into SRAM are commenced to be captured, before the input data are defined synchronizing with a rising or a falling of a signal which inactivates the write enable signal.
One of the specifications needed for use of the general-purpose SRAM is an address hold time (Twr). The address hold time Twr defines a time duration, in which the external address presenting the access address has to be held at the same value after the write enable signal has been inactivated. Normally, the general-purpose SRAM may be configured to define zero second as the minimum value of the address hold time Twr.
The conventional pseudo SRAM performs the control to the refresh operation without sufficient consideration of a relationship between a timing of transition of the write enable signal and another timing of transition of the external address signal. For this reasons, immediately after the data write operation (the inactivation of the write enable signal) has been completed, the refresh operation may be commenced. In this case, it is possible that the external access address overlaps an internally generated refresh address.
This point is particularly remarkable problem in such a configuration that any transition of the address signal is detected for the refresh operation. One countermeasure may be considered that the external address is so defined to remain for a period of time after the write enable signal has been inactivated. In this case, however, the address hold time Twr is defined, for example, in a few nanoseconds to several tends nanoseconds. This has a large difference from the general-purpose SRAM which normally ensures zero second. There is an issue to change the configuration of using the semiconductor memory device.
The present invention was made in the above points of view. An object of the present invention is to provide a semiconductor memory device with memory cells comprising DRAM, wherein such problems are not raised that the refresh provides an influence to the normal access, and that the refresh operation is not permitted by continuous data write operations, and wherein the semiconductor memory device ensures conditions in use as closely to the general-purpose SRAM as possible, and another object thereof is to provide a refresh control circuit thereof. Particularly, an object of the present invention is to provide a semiconductor memory device and a refresh control circuit, which allow the specification of the address hold time Twr for data write operation to be defined equivalent to that of the general-purpose SRAM.
In order to solve the above issues, the present invention provides a semiconductor memory device comprising: a memory cell array having a plurality of memory cells which need refresh; an access circuit for making an access to a memory cell designated by an access address externally supplied; a refresh clock signal generating circuit for generating a refresh clock signal which provides a reference to a time interval of refresh operations; an address transition detecting circuit for detecting a transition of the access address and generating an access address transition detecting signal; and a control circuit for activating a refresh enable signal for enabling a refresh operation based on a generation of the access address transition detecting signal by triggering the refresh clock signal, and for executing a refresh to a memory cell corresponding to a refresh address by triggering the generation of the access address transition detecting signal, prior to executing an access to a memory cell designated by the access address.
After the control circuit executes the refresh operation in a state that the refresh enable signal is activated, then the control circuit may inactivate the refresh enable signal in only a predetermined period of time based on the refresh clock signal, so that the control circuit discontinues the refresh operation by triggering the generation of the access address transition detecting signal.
The control circuit may be adopted to execute a refresh operation by triggering an input of a write instruction signal, independently from the refresh enable signal, before the control circuit executes a write operation to a memory cell designated by the access address.
The control circuit may be adopted to execute a refresh operation by triggering the write instruction signal and a subsequent write operation if the write instruction signal is inputted within a predetermined period of time which is defined to correspond to a maximum value of a time interval of transitions of the access address to the memory cells, and the predetermined period of time starts from a time of generation of the refresh clock signal.
If the control circuit executes the refresh by triggering the write instruction signal and the subsequent write operation, then the control circuit may be adopted to not activate the refresh enable signal by triggering a next-generated refresh clock signal, and upon an input of the access address transition detecting signal, the control circuit makes an access to a memory cell designated by the access address without refresh operation.
A time interval of transitions of the access address to the memory cell may be shorter than a cycle of the refresh clock signal.
An input circuit for inputting a chip select signal which selects the semiconductor memory device may further be provided, where the chip select signal is supplied externally; and the address transition detecting circuit detects either a transition of the access address to the memory cell, and the access address being supplied externally, or a transition of a chip select signal for generating the access address transition detecting signal.
A write instruction signal may be a pulse signal with a predetermined pulse width, and data of the memory cell are defined at an end timing of rising or falling of the pulse signal.
If any transition of the access address to the memory cell is not caused in a predetermined period of time based on the refresh clock signal, then the control circuit may be adopted to execute refresh operations to a memory cell corresponding to the refresh address at a predetermined cycle based on the refresh clock signal.
The present invention also provides a semiconductor memory device comprising: a memory cell array having a plurality of memory cells which need refresh; an access circuit for making an access to a memory cell designated by an access address externally supplied; a refresh address generating circuit for generating a refresh address which designates a memory cell being subject to refresh; and a control circuit executing a data read operation to a memory cell designated by the access address after a predetermined time has passed from a transition of the access address, and for subsequently executing a refresh operation of a memory cell corresponding to the refresh address, and for further executing a data write operation to a memory cell designated by the access address.
The present invention also provides a refresh operation control circuit for controlling refresh operations to memory cells, wherein the refresh operation control circuit generates a refresh clock signal which provides a reference to a time interval of refresh operations, and wherein the refresh operation control circuit controls executing a refresh operation generated in response to a transition of an access address by the refresh clock signal.
After the refresh operation is executed in response to a transition of the access address, then the refresh operation in response to the transition of the access address may not be executed in a predetermined period of time based on the refresh clock signal.
A refresh operation may be executed by triggering an input of a write instruction signal, independently from the refresh enable signal.
A refresh operation may be executed by triggering the write instruction signal if the write instruction signal is inputted within a predetermined period of time which is defined to correspond to a maximum value of a time interval of transitions of the access address to the memory cells, and the predetermined period of time starts from a time of generation of the refresh clock signal.
If the refresh is executed by triggering the write instruction signal and subsequently the refresh clock signal is generated, then a refresh operation in response to a transition of the access address may be omitted.
A time interval of transitions of the access address to the memory cell may be shorter than a cycle of the refresh clock signal.
If any transition of the access address to the memory cell is not caused in a predetermined period of time based on the refresh clock signal, then refresh operations may be executed at a predetermined cycle based on the refresh clock signal.